BCD subtractor is a circuit which accepts minuend and subtrahend in the form of BCD and produces the difference in BCD form. The BCD subtractor will be implemented in this project with the help of a BCD adder and 9’s complement circuits. A schematic diagram of the design of the BCD Subtractor is shown in figure (1).

Must Read BCD Adder Circuit

Table of Contents

## Project

## Circuit Diagram

## Components Required

- 7483 4 Bit Adder (x4)
- 7404 NOT Gate (x2)
- 7432 OR Gate
- 7485 Magnitude Comparator
- 7486 EX-OR Gate
- Single Pole 2-Way Switch (x8)
- LED (x5)
- 5V Power Supply
- Breadboard
- Wires

## About Parts

### IC-7486 EX-OR Gate

This is a Quad 2-input EX-OR gate with 14 pins IC. It is widely used in the arithmetic section of a computer. This gate is widely used in digital electronics design and therefore, is available in IC form. EX-OR has two inputs and an output. Output is 1 (High) only when the inputs are unequal and output is 0 (Low) when the inputs are the same. If this acts as an inequality detector. The pin diagram of the IC-7486 is shown in figure (2).

#### Truth table for IC-7486 X-OR Gate

Inputs | Outputs |

A | B | Y=A⊕B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 0 |

### IC-7483 4-Bit Full Adder

The IC-7483 is a commonly available TTL 4-bit parallel adder chip. It contains four interconnected full adders; a look-ahead carry circuitry for its operation (CLA = Carry Look-Ahead Adder). The logic symbol of IC-7483 is shown in figure (3) and the pin configuration in table 1. It has two 4-bit A3, A2, A1, A0 and B3, B2, B1, B0 and a carry input Cin in the LSB stage. The outputs are a 4-bit sum S3, S2, S1, S0 and a carry output (C_{out}) from the MSB stage.

Two or more parallel adder blocks can be connected in a cascade to perform the addition operation on a larger binary number. The four LSB of the number is added in the first adder. The carry output of this adder is given as carrying input to the second adder, which adds the four MSB of the number. the output carry of the second adder is the final carry output.

### IC-7404 NOT Gate

The IC-7404 is a logic gate IC. It consists of six NOT gates. We know that the NOT gate is also called an inverter because it does complement of the input. When we apply zero or low signal to the input, it gives 1 or high signal as in the output. The pin diagram of the IC-7404 is shown in figure (4).

#### Truth table for IC-7404 NOT Gate

Inputs | Outputs |
---|---|

X | x̄ |

0 | 1 |

1 | 0 |

### IC-7485 4 bit Comparator

The IC-7485 is a 4-bit magnitude comparator of the TTL family. This IC compares the magnitudes of two 4-bit numbers; A3, A2, A1, A0. and B3, B2, B1, B0. This IC has three outputs (A>B)_{out}, (A=B)_{out}, and (A<B)_{out}. Besides those pins, this IC has cascading facilities. These cascading inputs are (A>B)_{in}, (A=B)_{in}, and (A<B)_{in}. When the two inputs are equal then the outputs of the chip become a function of cascading inputs.

### IC-7432 OR Gate

The IC-7432 is a member of gate ICs and has the functionality of an OR gate or function. It will give high if either all or any one of the two inputs is high. IC-7432 has 4 OR gates of 2 inputs in 1 package. The internal gates are made of from Schottky Transistor of low power.

## Circuit Connection for BCD Subtractor Circuit

- Firstly, for the 1st 9’s complement circuit we use the NOT Gate (IC-7404) and CLA (carry look-ahead) Adder IC (IC-7483).
- Secondly, for the middle BCD Adder part, we use two (IC-7483) CLA Adder, (IC-7485) 4-bit Magnitude comparator and one (IC-7432) OR Gate.
- Thirdly, for the last part i.e. 2nd 9’s complement circuit, we use the X-OR Gate (IC-7486) and CLA Adder IC (IC-7483).

## PCB Design

For removing messy wiring and give a clean look, I designed a PCB prototype for this project. It is also helpful for troubleshooting that runs great without any errors. To design this PCB board, I used EasyEDA as it is too easy to use. For ordering PCB for this, I prefer PCBWay.

Gerber file for **BCD subtractor Circuit Gerber**.

You can view the Gerber file here **Gerber File Viewer**.

**PCB View**

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## Working Principle of BCD Subtractor Circuit

The working principle of this project is quite complicated, so read this carefully. In subtractor, one 9’s complement circuit is used to produce the 9’s complement of the BCD subtrahend Y (Y3 Y2 Y1 Y0). The output of the 9’s complement circuit is used as one of the two inputs of the BCD adder. The other input of this BCD adder is connected directly to the BCD minuend. The second 9’s complement circuit is connected to the sum of the output of the BCD adder which generates the 9’s complement of the BCD adder output if the EN(=Cout) input of the second 9’s complement circuit is 1 otherwise for EN=0 i.e., C_{out} = 1, the 9’s complement circuit passes the sum output of the BCD adder unchanged. This type of 9’s complement circuit is shown below.

The action of this single decade BCD subtractor can be understood from the following discussion.

There may be two cases that may arrive:

- BCD minuend (X) ≤ BCD subtrahend (Y)
- BCD minuend (X) > BCD subtratend

In both cases,

A input of the BCD adder = Minuend = X

B input of the BCD adder = 9’s complement of the subtrahend = 9-Y

**Case (1):** X≤Y

Sum output of the BCD adder. Then X + (9- Y) + Cin + BCD correction factor (if needed).

As X≤Y, the sum X+ (9-Y) can never exceed 9 because the maximum value of X and y is 9.

Therefore, carry output from the BCD adder = C_{out}=0 and hence, carry input C_{in} is 0 and as C_{in} and C_{out} are connected.

The BCD correction in the adder unit is not needed when C_{out} = 0 because the sum from the full adder unit of this BCD adder is X+(9-Y)≤9.

The enable input (EN) of the second 9’s complement circuit = C_{out}=1, so the output of the second 9’s complement generator circuit is 9-{X+(9-Y)} = (Y-X).

Hence, the output of the 9’s complement circuit gives the magnitude and the output of the NOT Gate is 1. This output indicates the negative sign.

**Case (2):** X>Y

In this case, the sum X+(9-Y) always exceeds 9, so the BCD correction factor within the BCD adder will be 6.

Carry output from the BCD adder is C_{out}=1 and hence the C_{in}=1.

Sum output of the BCD adder= X+(9-Y) +1+6 = (X-Y)+16.

The factor 16 indicates that C_{out}=1. If this Cout is ignored then the sum output from the BCD adder will be (X-Y) and as C_{out}=1, the enable input of the second 9’s complement circuit is 0. Therefore, the output of this 9’s complement circuit will be (X-Y).

#### Theoretical truth table for subtraction of two BCD number and getting the result in BCD

BCD Inputs | BCD Result Output |

X(Inputs) | Y(Inputs) | S |

X_{3} | X_{2} | X_{1} | X_{0} | Y_{3} | Y_{2} | Y_{1} | Y_{0} | EN(sign) | S_{3} | S_{2} | S_{1} | S_{0} | Remarks |

0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | No sign |

1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | bit generated |

1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | (Result is |

1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | +ve) |

0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | Sign bit is |

0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | generated |

0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | (Result is in -ve) |

0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |

#### Experimental truth table for subtraction of BCD numbers:

BCD Input(X) | BCD Input(Y) | EN | BCD Output |

X | Y | S |

X_{3} | X_{2} | X_{1} | X_{0} | Y_{3} | Y_{2} | Y_{1} | Y_{0} | EN (sign) | S_{3} | S_{2} | S_{1} | S_{0} |

0.15 | 0.15 | 5.05 | 5.05 | 0.15 | 0.15 | 5.05 | 0.15 | OFF | OFF | OFF | OFF | ON |

5.05 | 0.15 | 0.15 | 0.15 | 0.15 | 0.15 | 5.05 | 5.05 | OFF | OFF | ON | OFF | ON |

5.05 | 5.05 | 5.05 | 5.05 | 0.15 | 0.15 | 5.05 | 0.15 | OFF | ON | ON | OFF | ON |

5.05 | 5.05 | 0.15 | 5.05 | 0.15 | 0.15 | 5.05 | 5.05 | OFF | ON | OFF | ON | OFF |

0.15 | 0.15 | 5.05 | 5.05 | 5.05 | 5.05 | 5.05 | 5.05 | ON | ON | ON | OFF | OFF |

0.15 | 0.15 | 0.15 | 5.05 | 5.05 | 0.15 | 5.05 | 5.05 | ON | ON | OFF | ON | OFF |

0.15 | 0.15 | 0.15 | 0.15 | 0.15 | 0.15 | 0.15 | 5.05 | ON | OFF | OFF | OFF | ON |

0.15 | 0.15 | 5.05 | 0.15 | 0.15 | 5.05 | 5.05 | 0.15 | ON | OFF | ON | OFF | OFF |

## Conclusion for BCD Subtractor Circuit

Therefore comparing the experimental tables with theoretical tables i.e., table(1) and table (2), we can conclude that our experiment of BCD subtractor and getting the result in BCD form, by using a BCD adder within this and correction circuit is verified and successfully implemented by using 9’s complement circuit and BCD adder with correction circuit using IC-7485. Noted that the sign bit is ‘LOW’ for a positive result and ‘HIGH’ for a negative result.

## Precautions and Discussions for BCD Subtractor Circuit

- Various resistance should be chosen in the conduction state current through the LED. So that it doesn’t exceed the maximum rated current. So carefully choose the safety resistance.
- The experiment has been done by using +ve level logic where a high voltage i.e. equal to (+V
_{CC}) i.e., +5v is taken as ‘1’ and a low voltage i.e., equal to GND i.e., 0V is taken as ‘0’. - LEDs with proper current limiting resistance can be used for easy, quick and visual identification of ‘0’ and ‘1’ states. If the LED glow then it is in an on state and if it doesn’t glow then it is in an off state.
- While connecting the 5V DC supply to the IC special care should be taken. Connection to any wrong pin any damage maybe happen.
- Carefully connect the pins bitwise from comparators IC-7485 and IC-7483. For any wrong correction, the output will not be as we want to get.
- For the BCD Subtractor circuit, we are using two 9’s complement circuits, one at the first point i.e., before the BCD adder and the other is just after the BCD adder circuit.
- Special care should be taken during setting up the wire connection to LSB and MSB bit so that the output should be in the correct form otherwise it goes wrong.