Design And Implementation of a BCD Adder Circuit Using IC-7483

In this project, we are implementing and designing a BCD Adder circuit using IC-7483. The objective of this experiment is to fully understand and implement of addition of two BCD numbers and get the result in BCD form.

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This arithmetic circuit accepts two BCD numbers as the augend and addend at its two 4-bit inputs and produces their sum in the same code (BCD code). The BCD adder is usually complicated compared to the binary adder. Because of the fact that some of the sum outputs don’t belong to the group of BCD codes. If the sum of the two BCD inputs along with a carry-in bit gives the decimal 9 (1001) or less, then the sum represents the valid BCD sum. But the problem arises if the sum exceeds BCD codes of decimal 9.

Since each input BCD digit may be a maximum of 9, then considering an input carry of 1, the sum of the two BCD digits may be a maximum of 19 = (9+9+1). But the sum which is greater or equal to decimal 10 but less than or equal to decimal 19 can’t be represented by a 4-Bit valid BCD code. It requires two 4-Bit groups of valid BCD code. For example, consider the sum of 3+9.

3 {0011} + 9 {1001} = 12 {1100}

The resulting sum 1100 is not a valid BCD code of decimal 12. The correct answer should be 0001 0010. The below table shows the corrected BCD for all possible sum outputs from a 4-bit binary adder, adding BCD augend and addend. It may be noted from the table that the corrected BCD form can be obtained from the sum output simply by adding 6 (0110) to it when the sum is greater than 9 but less or equal to 19.

Project

BCD Adder circuit

Circuit Diagram

BCD Adder Circuit Diagram
BCD Adder Circuit Diagram

Components Required

  • 7483 Adder IC (x2)
  • 7485 Comparator IC
  • 7404 NOT Gate IC
  • 3 Terminal Switch (x8)
  • 4 LED (S3-S0)
  • LSB LED
  • +5V Power Supply
  • Breadboard
  • Wires

Circuit Connection of BCD Adder Circuit

Now we can use IC-7485, the 4-bit magnitude comparator and an OR gate shown in Fig 1 to make the correction circuit. One 4-bit input (B3, B2, B1, B0) of the comparator is connected to 1001 (910), and the other 4-bit input (A3, A2, A1, A0) of the comparator is connected to the outputs (S3, S2, S1, S0) of the full adder, FA1. The (A>B) output of the comparator and the Cout of the FA1 adder is connected with the OR gate inputs. The output of the OR gate is connected to the B1 and B2 input of the FA2 full adder. Finally, connect B3 and B0 with the ground.

When the sum output S3‘, S2‘, S1‘, S0‘ is greater than 910 or Cout of FA1 is 1, the OR gate output becomes 1 for which 0110 is added with S3‘, S2‘, S1‘, S0‘ by the FA2 because B2 and B1 both become 1 under this situation. But the comparator output (A>B) = 0 and Cout = 0 (the carry-out of FA1) when the sum output from (full adder)1 is less than 9 or maximum equal to 9. Therefore the B1 and B2 inputs of (full adder)2 are 0 and no correction is done because 0000 is added to (S3‘, S2‘, S1‘, S0‘) by (full adder)2.

ICs Used for Making The BCD Adder Circuit

IC-7483 (4-Bit Binary Adder)

The IC-7483 is a commonly available TTL 4-bit parallel adder chip. It contains four interconnected full adders; a look-ahead carry circuitry for its operation (CLA = Carry Look-Ahead Adder). The logic symbol of IC7483 is shown in fig 2 and the pin configuration in table 1. It has two 4-bit A3, A2, A1, A0 and B3, B2, B1, B0 and a carry input Cin in the LSB stage. The outputs are a 4-bit sum S3, S2, S1, S0 and a carry output (Cout) from the MSB stage.

Two or more parallel adder blocks can be connected in a cascade to perform the addition operation on a larger binary number. The four LSB of the number is added in the first adder. The carry output of this adder is given as carrying input to the second adder, which adds the four MSB of the number. the output carry of the second adder is the final carry output.

IC-7485 (4-Bit Magnitude Comparator)

The IC-7485 is a 4-bit magnitude comparator of the TTL family. The circuit diagram is shown in fig 3. This IC compares the magnitudes of two 4-bit numbers; A3, A2, A1, A0. and B3, B2, B1, B0. This IC has three outputs (A>B)out; (A=B)out and (A<B)out. Besides those pins, this IC has cascading facilities. These cascading inputs are (A>B)in; (A=B)in and (A<B)in. When the two inputs are equal then the outputs of the chip become a function of cascading inputs.

IC-7432 (OR Gate)

The IC-7432 is a member of gate ICs and has the functionality of an OR gate or function. It will give high if either all or any one of the two inputs is high. IC-7432 has 4 OR gates of 2 inputs in 1 package. The internal gates are made of from Schottky Transistor of low power.

PCB Design

For removing messy wiring and give a clean look, I designed a PCB prototype for this project. It is also helpful for troubleshooting that runs great without any errors. To design this PCB board, I used EasyEDA as it is too easy to use. For ordering PCB for this, I prefer PCBWay.

Gerber file for BCD Adder Circuit Gerber.

You can view the Gerber file here Gerber File Viewer.

PCB View

BCD Adder Circuit 2D View
2D View
BCD Adder Circuit 3D View
3D View

Order PCB From PCBWay

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Guide for Ordering PCB From PCBWay

Truth Tables for BCD Adder Circuit

Table 1: Truth table for comparator IC-7485

ABY (A>B)Y(A=B)Y (A<B)
00100
01001
10010
11100

Where A and B are inputs and all three Y’s values are outputs.

Table 2: Theoretical truth table for binary and corrected BCD numbers

Sum In DecimalSum Output From A 4-Bit Binary FA1
After the addition of Two BCD Numbers
Decimal No.C3′S3′S2′S1′S0′COUTS3S2S1S0
00000000000
10000100001
20001000010
30001100011
40010000100
50010100101
60011000110
70011100111
80100001000
90100101001
100101010000
110101110001
120110010000
130110110001
140111010110
150111110111
161000010110
171000110111
181001011000
191001111001

Example

BCD adder circuit 2
BCD adder circuit 3

Table 3: Theoretical truth table for the addition of two BCD numbers and getting the result in BCD [Cin=0 and Cin=1 in both cases]

BCD InputsBCD Outputs
CinB3B2B1B0A3A2A1A0CoutS3S2S1S0
00010001100101
00001001100100
10011010001000
10100010001001
01000100110111
01000001110001
10100100110100
11001100111001

Table 2 shows the correction is needed under the following condition:-

  • If the carry out of the 4-bit binary full adder is 1 after the addition of two BCD digits.
  • If the sum bits S2‘ and S3‘ of the binary full adder are such that S2‘S3‘=1.
  • If the sum bits S1‘ and S3‘ of the binary full adder are such that S1‘S3‘=1.

These three conditions can be combined to form an expression as

X = C3‘+S2‘S3‘+S1‘S3

This expression for X shows that if X=1 then we used to take the help of BCD correction (by adding 6 to the valid BCD). Based on this expression we may design a correction circuit which will produce (x=1) when the sum output is not a valid BCD and adds 6 (0110) to the invalid BCD output from the binary adder. When this correction circuit produces X=0, then the sum output from the adder is less than or equal to 9 and no correction is required.

Table 4 for OR Gate used within the circuit configuration (IC-7432)

InputsOutputs
ABY=A+B
000
011
101
111

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