In this project, we are implementing and designing a BCD Adder circuit using IC-7483. The objective of this experiment is to fully understand and implement of addition of two BCD numbers and get the result in BCD form.

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This arithmetic circuit accepts two BCD numbers as the augend and addend at its two 4-bit inputs and produces their sum in the same code (BCD code). The BCD adder is usually complicated compared to the binary adder. Because of the fact that some of the sum outputs don’t belong to the group of BCD codes. If the sum of the two BCD inputs along with a carry-in bit gives the decimal 9 (1001) or less, then the sum represents the valid BCD sum. But the problem arises if the sum exceeds BCD codes of decimal 9.

Since each input BCD digit may be a maximum of 9, then considering an input carry of 1, the sum of the two BCD digits may be a maximum of 19 = (9+9+1). But the sum which is greater or equal to decimal 10 but less than or equal to decimal 19 can’t be represented by a 4-Bit valid BCD code. It requires two 4-Bit groups of valid BCD code. For example, consider the sum of 3+9.

3 {0011} + 9 {1001} = 12 {1100}

The resulting sum of 1100 is not a valid BCD code of decimal 12. The correct answer should be 0001 0010. The below table shows the corrected BCD for all possible sum outputs from a 4-bit binary adder, adding BCD augend and addend. It may be noted from the table that the corrected BCD form can be obtained from the sum output simply by adding 6 (0110) to it when the sum is greater than 9 but less or equal to 19.

## Project

## Circuit Diagram

## Components Required

- 7483 Adder IC (x2)
- 7485 Comparator IC
- 7404 NOT Gate IC
- 3 Terminal Switch (x8)
- 4 LED (S3-S0)
- LSB LED
- +5V Power Supply
- Breadboard
- Wires

## Circuit Connection of BCD Adder Circuit

Now we can use IC-7485, the 4-bit magnitude comparator and an OR gate shown in Fig 1 to make the correction circuit. One 4-bit input (B_{3}, B_{2}, B_{1}, B_{0}) of the comparator is connected to 1001 (9_{10}), and the other 4-bit input (A_{3}, A_{2}, A_{1}, A_{0}) of the comparator is connected to the outputs (S_{3}, S_{2}, S_{1}, S_{0}) of the full adder, FA_{1}. The (A>B) output of the comparator and the C_{out} of the FA_{1} adder is connected with the OR gate inputs. The output of the OR gate is connected to the B_{1} and B_{2} input of the FA_{2} full adder. Finally, connect B_{3} and B_{0 with the }ground.

When the sum output S_{3}‘, S_{2}‘, S_{1}‘, S_{0}‘ is greater than 9_{10} or C_{out} of FA_{1} is 1, the OR gate output becomes 1 for which 0110 is added with S_{3}‘, S_{2}‘, S_{1}‘, S_{0}‘ by the FA_{2} because B2 and B1 both become 1 under this situation. But the comparator output (A>B) = 0 and C_{out} = 0 (the carry-out of FA_{1}) when the sum output from (full adder)_{1} is less than 9 or maximum equal to 9. Therefore the B1 and B2 inputs of (full adder)_{2} are 0 and no correction is done because 0000 is added to (S_{3}‘, S_{2}‘, S_{1}‘, S_{0}‘) by (full adder)_{2}.

## ICs Used for Making The BCD Adder Circuit

**IC-7483 (4-Bit Binary Adder****)**

The IC-7483 is a commonly available TTL 4-bit parallel adder chip. It contains four interconnected full adders; a look-ahead carry circuitry for its operation (CLA = Carry Look-Ahead Adder). The logic symbol of IC7483 is shown in fig 2 and the pin configuration in table 1. It has two 4-bit A_{3}, A_{2}, A_{1}, A_{0} and B_{3}, B_{2}, B_{1}, B_{0} and a carry input C_{in} in the LSB stage. The outputs are a 4-bit sum S_{3}, S_{2}, S_{1}, S_{0} and a carry output (C_{out}) from the MSB stage.

Two or more parallel adder blocks can be connected in a cascade to perform the addition operation on a larger binary number. The four LSB of the number is added in the first adder. The carry output of this adder is given as carrying input to the second adder, which adds the four MSB of the number. the output carry of the second adder is the final carry output.

**IC-7485 (4-Bit Magnitude Comparator)**

The IC-7485 is a 4-bit magnitude comparator of the TTL family. The circuit diagram is shown in fig 3. This IC compares the magnitudes of two 4-bit numbers; A_{3}, A_{2}, A_{1}, A_{0}. and B_{3}, B_{2}, B_{1}, B_{0}. This IC has three outputs (A>B)_{out}; (A=B)_{out} and (A<B)_{out}. Besides those pins, this IC has cascading facilities. These cascading inputs are (A>B)_{in}; (A=B)_{in} and (A<B)in. When the two inputs are equal then the outputs of the chip become a function of cascading inputs.

**IC-7432 (OR Gate)**

The IC-7432 is a member of gate ICs and has the functionality of an OR gate or function. It will give high if either all or any one of the two inputs is high. IC-7432 has 4 OR gates of 2 inputs in 1 package. The internal gates are made of from Schottky Transistor of low power.

## Truth Tables for BCD Adder Circuit

**Table 1: Truth table for comparator IC-7485**

A | B | Y (A>B) | Y(A=B) | Y (A<B) |
---|---|---|---|---|

0 | 0 | 1 | 0 | 0 |

0 | 1 | 0 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 1 | 1 | 0 | 0 |

Where A and B are inputs and all three Y’s values are outputs.

**Table 2: Theoretical truth table for binary and corrected BCD numbers**

Sum In Decimal | Sum Output From A 4-Bit Binary FA_{1}After the addition of Two BCD Numbers |

Decimal No. | C3′ | S3′ | S2′ | S1′ | S0′ | C_{OUT} | S3 | S2 | S1 | S0 |
---|---|---|---|---|---|---|---|---|---|---|

0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |

2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |

3 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |

4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |

5 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |

6 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |

7 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |

8 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |

9 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 |

10 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |

11 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |

12 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |

13 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 |

14 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |

15 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |

16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |

17 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |

18 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |

19 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |

## Example

**Table 3: Theoretical truth table for the addition of two BCD numbers and getting the result in BCD [C**_{in}=0 and C_{in}=1 in both cases]

_{in}=0 and C

_{in}=1 in both cases]

BCD Inputs | BCD Outputs |

C_{in} | B_{3} | B2 | B1 | B0 | A3 | A2 | A1 | A0 | C_{out} | S3 | S2 | S1 | S0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|

0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |

0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |

1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |

0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 |

0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |

1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 |

Table 2 shows the correction is needed under the following condition:-

- If the carry out of the 4-bit binary full adder is 1 after the addition of two BCD digits.
- If the sum bits S
_{2}‘ and S_{3}‘ of the binary full adder are such that S_{2}‘S_{3}‘=1. - If the sum bits S
_{1}‘ and S_{3}‘ of the binary full adder are such that S_{1}‘S_{3}‘=1.

These three conditions can be combined to form an expression as

**X = C _{3}‘+S_{2}‘S_{3}‘+S_{1}‘S_{3}‘**

This expression for X shows that if X=1 then we used to take the help of BCD correction (by adding 6 to the valid BCD). Based on this expression we may design a correction circuit that will produce (x=1) when the sum output is not a valid BCD and adds 6 (0110) to the invalid BCD output from the binary adder. When this correction circuit produces X=0, then the sum output from the adder is less than or equal to 9 and no correction is required.

**Table 4 for OR Gate used within the circuit configuration (IC-7432)**

Inputs | Outputs |

A | B | Y=A+B |
---|---|---|

0 | 0 | 0 |

0 | 1 | 1 |

1 | 0 | 1 |

1 | 1 | 1 |